The present invention relates to electronic circuits that retain identical functionality and improved performance and power under Random Access Memory (RAM) and Hard-Wire Read Only Memory (ROM) fabrication options.
Traditionally, application specific integrated circuit (ASIC) devices have been used in the integrated circuit (IC) industry to reduce cost, enhance performance or meet space constraints. The generic class of ASIC devices falls under a variety of sub classes such as Custom ASIC, Standard cell ASIC, Gate Array and Field Programmable Gate Array (FPGA) where the degree of user allowed customization varies. In this disclosure the word ASIC is used only in reference to Custom and Standard Cell ASICs where the designer has to incur the cost of a full fabrication mask set. The term FPGA denotes an off the shelf programmable device with no fabrication mask costs, and Gate Array denotes a device with partial mask costs to the designer. The devices FPGA include Programmable Logic Devices (PLD) and Complex Programmable Logic Devices (CPLD), while the devices Gate Array include Laser Programmable Gate Arrays (LPGA), Mask Programmable Gate Arrays (MPGA) and a new class of devices known as Structured ASIC or Structured Arrays.
The design and fabrication of ASICs can be time consuming and expensive. The customization involves a lengthy design cycle during the product definition phase and high Non Recurring Engineering (NRE) costs during manufacturing phase. In the event of finding a logic error in the custom or semi-custom ASIC during final test phase, the design and fabrication cycle has to be repeated. Such lengthy correction cycles further aggravate the time to market and engineering cost. As a result, ASICs serve only specific applications and are custom built for high volume and low cost. The high cost of masks and unpredictable device life time shipment volumes have caused ASIC design starts to fall precipitously in the IC industry. ASICs offer no device for immediate design verification, no interactive design adjustment capability, and require a full mask set for fabrication.
Gate Array customizes pre-defined modular blocks at a reduced NRE cost by designing the module connections with a software tool similar to that in ASIC. The Gate Array has an array of non programmable (or moderately programmable) functional modules fabricated on a semiconductor substrate. To interconnect these modules to a user specification, multiple layers of wires are used during design synthesis. The level of customization may be limited to a single metal layer, or single via layer, or multiple metal layers, or multiple metals and via layers. The goal is to reduce the customization cost to the user, and provide the customized product faster. As a result, the customizable layers are designed to be the top most metal and via layers of a semiconductor fabrication process. This is an inconvenient location to customize wires. The customized transistors are located at the substrate level of the Silicon. All possible connections have to come up to the top level metal. The complexity of bringing up connections is a severe constraint for these devices. Structured ASICs fall into larger module Gate Arrays. These devices have varying degrees of complexity in the structured cell and varying degrees of complexity in the custom interconnection. The absence of Silicon for design verification and design optimization results in multiple spins and lengthy design iterations to the end user. The Gate Array evaluation phase is no different to that of an ASIC. The advantage over ASIC is in a lower upfront NRE cost for the fewer customization layers, tools and labor, and the shorter time to receive the finished product. Gate Arrays offer no device for immediate design verification, no interactive design adjustment capability, and require a partial mask set for fabrication. Compared to ASICs, Gate Arrays offer a lower initial cost and a faster turn-around to debug the design. The end IC is more expensive compared to an ASIC.
In recent years there has been a move away from custom, semi-custom and Gate Array ICs toward field programmable components whose function is determined not when the integrated circuit is fabricated, but by an end user “in the field” prior to use. Off the shelf FPGA products greatly simplify the design cycle and are fully customized by the user. These products offer user-friendly software to fit custom logic into the device through programmability, and the capability to tweak and optimize designs to improve Silicon performance. In an FPGA, a complex logic design is broken down to smaller logic blocks and programmed into logic blocks provided in the FPGA. Logic blocks contain multiple smaller logic elements. Logic elements facilitate sequential and combinational logic design implementations. Combinational logic has no memory and outputs reflect a function solely of present input states. Sequential logic is implemented by inserting memory in the form of a flip-flop into the logic path to store past history. Current FPGA architectures include transistor pairs, NAND or OR gates, multiplexers, look-up-tables (LUT) and AND-OR structures in a basic logic element. In a PLD the basic logic element is labeled a macro-cell. Hereafter the terminology logic element will include both logic elements and macro-cells.
For sequential logic designs, the logic element may also include flip-flops. A MUX based exemplary logic element described in Ref-1 (Seals & Whapshott) is shown in FIG. 1A. The logic element has a built in D-flip-flop 105 for sequential logic implementation. In addition, elements 101, 102 and 103 are 2:1 MUX's controlled by one input signal for each MUX. Input S1 feeds into 101 and 102, while inputs S1 and S2 feed into OR gate 104, and the output from OR gate feeds into 103. Element 105 is the D-Flip-Flop receiving Preset, Clear and Clock signals. One may very easily represent the programmable MUX structure in FIG. 1A as a 2-input LUT; where A, B, C & D are LUT values, and S1, (S2+S3) are LUT inputs. Ignoring the global Preset & Clear signals, eight inputs feed into the logic block, and one output leaves the logic block. All 2-input, all 3-input and some 4-input variable functions are realized in the logic block and latched to the D-Flip-Flop. Inputs and outputs for the Logic Element or Logic Block are selected from the programmable Routing Matrix. An exemplary routing matrix containing logic elements as described in Ref-1 is shown in FIG. 1B. Each logic element 112 is as shown in FIG. 1A. The 8 inputs and 1 output from logic element 112 in FIG. 1B are routed to 22 horizontal and 12 vertical interconnect wires that have programmable via connections 110. These connections 110 may be anti-fuses or pass-gate transistors controlled by SRAM memory elements. The user selects how the wires are connected during the design phase, and programs the connections in the field. FPGA architectures for various commercially available FPGA devices are discussed in Ref-1 (Seals & Whapshott) and Ref-2 (Sharma).
Provision of this programmability is expensive in terms of Silicon real estate, but reduces design cycle time, time to solution (TTS) and upfront NRE cost to the designer. FPGAs offer the advantages of no NRE costs, fast turnaround (designs can be placed and routed on an FPGA in typically a few minutes), and low risk since designs can be easily amended late in the product design cycle. It is only for high volume production runs that there is a cost benefit in using the other two approaches. Compared to FPGA, an ASIC and Gate Array both have hard-wired logic connections, identified during the chip design phase. ASIC has no multiple logic choices and both ASIC and most Gate Arrays have no configuration memory to customize logic. This is a large chip area and a product cost saving for these approaches to design. The larger Silicon area for programmability in an FPGA causes two events that aggravate cost: larger chip area leads to less total available die in a wafer, larger chip area has a higher chance of having a defect that will make it non-functional. Of the two events, the former is proportional to die area while the latter is exponential to die area and dominates the cost of the product. A full custom ASIC has customized logic functions which take less gate counts compared to Gate Arrays and FPGA configurations of the same functions. Thus, an ASIC is significantly smaller, faster, cheaper and more reliable than an equivalent gate-count FPGA. A Gate Array is also smaller, faster and cheaper compared to an equivalent FPGA. The trade-off is between time-to-market (FPGA advantage) versus low cost and better reliability (ASIC advantage). A Gate Array falls in the middle with an improvement in the ASIC NRE cost at a moderate penalty to product cost and performance. The killer defects found in the extra area for programmability in an FPGA compared to ASIC and Gate Array contribute to a significant portion of the extra cost the user has to bear for customer re-configurability of logic functions. A method to reduce an FPGA final die cost would greatly enhance the cost parity between an FPGA and an ASIC.
FPGA and Gate Array architectures are discussed in Hartmann et al. (U.S. Pat. No. 4,609,986), Carter (U.S. Pat. No. 4,706,216), Turner et al. (U.S. Pat. No. 4,761,768), El-Ayat et al. (U.S. Pat. No. 4,857,774), Freeman (U.S. Pat. No. 4,870,302), El Gamal et al. (U.S. Pat. No. 4,873,459), Freeman et al. (U.S. Pat. No. 5,343,406), Freeman et al. (U.S. Pat. No. 5,488,316), Tsui et al. (U.S. Pat. No. 5,835,405), Trimberger et al. (U.S. Pat. No. 5,844,422), Wittig et al. (U.S. Pat. No 6,208,163), Or-Bach ( 2001/0003428), Mendel (U.S. Pat. No. 6,275,065), Or-Bach (U.S. Pat. No. 6,331,789), Young et al. (U.S. Pat. No. 6,448,808), Agrawal et al. (2002/0186044), Sueyoshi at al. (2003/0001615) and Pugh et al. (2003/0085733). These patents disclose programmable AND/OR array, MUX and LUT structures and routing blocks to build logic blocks that are user configurable. The configuration memory element comprises multiple transistors. SRAM memory has six transistors in a cell. Single poly EEPROM has three transistors, one capacitor and one tunneling diode in a cell. In all cases the memory element together with a configuration circuit allows the user to program the device. This programmable overhead creates a significant cost burden due to enhanced Silicon area and killer defects compared to a non-configurable solution. Addition of redundant circuits in an FPGA to repair some faulty circuits is not sufficient to reduce the cost disparity. There is no provision in the referenced disclosures for a user to get to a lower cost solution from an FPGA without having to re-engineer the entire design to either a Gate Array or an ASIC platform.
Logic elements include programmable point to point connections. Four exemplary methods of programmable point to point connections, synonymous with programmable switches, between node A and node B are shown in FIG. 2. Configuration circuits to program connections are shown in FIG. 3, FIG. 4 and FIG. 5. All the patents listed under FPGA architectures use one or more of these basic programmable connections. In FIG. 2A, a conductive fuse link 210 connects A to B. It is normally connected, and passage of a high current or exposure to a laser beam will blow the conductor open. In FIG. 2B, a capacitive anti-fuse element 220 disconnects A from B. It is normally open, and passage of a high current will pop the insulator shorting the two terminals. Fuse and anti-fuse are both one time programmable due to the non-reversible nature of the change. In FIG. 2C, a pass-gate device 230 connects A to B. The gate signal S0 determines the nature of the connection, on or off. This is a non destructive change. The gate signal is generated by manipulating logic signals, or by configuration circuits that include memory. The choice of memory varies from user to user. In FIG. 2D, a floating-pass-gate device 240 connects A to B. Control gate signal S0 couples a portion of that to floating gate. Electrons trapped in the floating gate determines an on or off state for the connection. Hot-electrons and Fowler-Nordheim tunneling are two mechanisms for injecting charge to floating-gates. When high quality insulators encapsulate the floating gate, trapped charge stays for over 10 years. These provide non-volatile memory. EPROM, EEPROM and Flash memory employ floating-gates and are non-volatile. Anti-fuse and SRAM based architectures are widely used in commercial FPGA's, while EPROM, EEPROM, anti-fuse and fuse links are widely used in commercial PLD's. Volatile SRAM memory needs no high programming voltages, is freely available in every logic process, is compatible with standard CMOS SRAM memory, lends to process and voltage scaling and has become the de-facto choice for modern day very large FPGA device construction.
Most commercially available high density FPGA's use SRAM memory elements. A volatile six transistor SRAM based configuration circuit is shown in FIG. 3A. This is the SRAM of choice in the listed patents. Two inverters 303 and 304 connected back to back form the memory element. This memory element is a latch providing complementary outputs S0 and S0′. The latch can be constructed as full CMOS, R-load, PMOS load or any other. Power and ground terminals for the inverters are not shown in FIG. 3A. Access NMOS transistors 301 and 302, and access wires GA, GB, BL and BS provide the means to configure the memory element. Applying zero and one on BL and BS respectively, and raising GA and GB high enables writing zero into device 301 and one into device 302. The output S0 delivers a logic one. Applying one and zero on BL and BS respectively, and raising GA and GB high enables writing one into device 301 and zero into device 302. The output S0 delivers a logic zero. The SRAM construction may allow applying only a zero signal at BL or BS to write data into the latch. The SRAM cell may have only one access transistor 301 or 302. The SRAM latch will hold the data state as long as power is on. When the power is turned off, the SRAM bit needs to be restored to its previous state from an outside permanent memory. In the literature for programmable logic, this second non-volatile memory is also called configuration memory. Upon power up, an external or an internal CPU loads the external configuration memory to internal configuration memory locations. All of FPGA functionality is controlled by the internal configuration memory. The SRAM configuration circuit in FIG. 3A controlling logic pass-gate is illustrated in FIG. 3B. Element 350 represents the configuration circuit. The S0 output directly driven by the memory element shown in FIG. 3A drives the pass-gate 310 gate electrode. In addition to S0 output and the memory cell, power, ground, data-in and write-enable signals in 350 constitutes the SRAM configuration circuit. Write enable circuitry includes GA, GB, BL, BS signals shown in FIG. 3A.
For an emulation device, the cost of programmability is not the primary concern if such a device provides a migration path to a lower cost production solution. Today an FPGA migration to a Gate Array requires a new design to ensure timing closure. The FPGA and the Gate Array devices are completely different dies, manufactured with completely different mask sets, having identical functionality. A desirable migration path is to keep the timing of the original FPGA design intact. That would avoid valuable re-engineering time, prevent opportunity costs and save invaluable time to solution (TTS). Such a conversion is preferable in the same base die to avoid manufacturing logistics complexity, save on Silicon and system re-qualification costs and avoid implementation delays. Such a conversion should also realize a lower cost end product that is competitive with an equivalent standard cell ASIC or a Gate Array product in cost. Such an FPGA device will readily target applications that are cost sensitive, have short life cycles and demand medium volumes.